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  • PLL(锁相环) IP

    编号
    IP名称
    特性
    工艺
    量产状况
    应用
    手册
    下载
    1
    1.8GHz LC type Franctional-N PLL
    13/26/19.2MHz input; 1.8GHz/900MHz output; with 20MHz phase noise less than -153dBc/Hz and 200kHz step
    0.35um CMOS
    Silicon Proven
    RFID etc
    2
    2.4GHz Integer-N PLL with LC VCO
    1M~24MHz input; 2.4GHz Output; 3MHz Phase noise less than -145dBc/Hz
    0.25um CMOS
    Mass Production
    Bluetooth, Zigbee, Cordless-Phone; Walk talkie
    3
    2.4GHz Fractional-N PLL with LC VCO
    1M~24MHz input; 2.4GHz Output; 3MHz Phase noise less than -150dBc/Hz
    0.18um CMOS
    Mass Production
    2.4GHz Application; Zigbee, Cordless-Phone; Walk talkie
    4
    100MHz~220MHz LC Fractional-N PLL
    32.768kHz or 13MHz input; 60MHz to 110MHz PLL output; 3MHz phase noise less than -145dBc/Hz; with 3MHz phase noise less than -145dBc/Hz
    0.18um CMOS
    Mass Production
    FM Receiver, FM Transmitter, others
    5
    Sigma-Delta Fractional-N 3GHz to 4.5GHz PLL
    13/26MHz input; 3GHz to 4.5GHz VCO output; 20MHz phase noise less than -157dBc/Hz
    0.18um CMOS
    Mass Production
    GSM, EDGE, TD-SCDMA
    6
    ADPLL with 3GHz to 4.5GHz VCO
    Fully All Digital PLL with 26MHz reference clock and 3~4.5GHz VCO, with phase noise -160dBc/Hz@20MHz
    0.18um CMOS
    Silicon Proven
    GSM, EDGE, 3G etc
    7
    208MHz Ring type Integer-N PLL
    1~26MHz input, about 208MHz Ring Oscillator, 1MHz phase noise less than -100dBc/Hz
    0.18um CMOS
    Silicon Proven
    Clock generation
    8
    100MHz Ring type Integer-N PLL
    32.768kHz input, about 100MHz output, 1MHz phase noise less than -95dBc/Hz
    0.18um CMOS
    Mass Production
    Clock generation
    9
    DLL (Delay Locked Loop)
    DLL with programmable resolution and minimum 2ns resolution
    0.18um CMOS
    Silicon Proven
    Timing Synchronize
    10
    500MHz Ring PLL
    1~26MHz input, about 500MHz Ring Oscillator output, 1MHz phase noise less than -98dBc/Hz
    0.18um CMOS
    Silicon Proven
    Clock generation
    11
    1.8GHz FN-PLL
    Fully Integrated, Sigma Delta, Fractional-N PLL with 16 Bits Fractional Frequency Resolution
    55nm CMOS
    Silicon Proven
    Clock Generation
    12
    20MHz ~175MHz PLL
    Reference frequency 32.768KHz - 40MHz; output frequency 20MHz -175MHz;  Reference divider values 1-64;  Feedback divider values 1-4096; Output divider values 1-8
    55nm CMOS
    Silicon Proven
    Clock Generation
    13
    13GHz ~15GHz UHF PLL 
    LC VCO with 6.5GHz to 8GHz, PLL with I,Q differential output 13.75GHz to 15.5GHz using Freq. Doubler; Support both fractional‐N and Integer‐N modes; 
    IBM 90nm SiGe
    Tapeout
    UHF Radar